The present invention relates generally to frequency synthesizers and synthesizing methods, and more particularly, to a wide bandwidth, low noise, fine frequency step phase locked loop frequency synthesizer and synthesizing method that provides for a large number of frequency steps.
Frequency synthesizers are used to generate reference frequencies for radar systems, communication systems, test instruments and numerous other devices. In many of these applications, there is a need for low phase noise and frequency agility. In general, frequency synthesizers include a signal source, a frequency multiplier or divider and a phase locked loop. The signal source (typically a crystal oscillator) provides a signal at a reference frequency. The frequency multiplier or divider uses this signal to synthesize a signal at a frequency of interest. The phase locked loop synchronizes the signal at the frequency of interest with an input signal.
Noise around a signal may be represented as fluctuations of either the amplitude or phase of the carrier. This noise is commonly referred to as phase noise, since fluctuations in phase are typically the dominant source of noise close to the carrier. Phase noise causes lower receiver sensitivity in multi-signal environments, clutter noise in Doppler radar systems, and phase errors in digital communication systems. Phase noise imposes fundamental limitations wherever a weak signal is processed in the presence of a strong interfering signals. In receivers, phase noise sidebands of the receiver local oscillator are transferred to the IF product of the strong interfering signal and cover up the weak wanted signals. In a Doppler radar system, the strong interfering signal is produced by reflections from large stationary objects. Phase noise side bands of this unwanted return signal are decorrelated by delay and potentially cover the weak Doppler signal in the form of clutter noise. Phase noise is also a limiting factor in digital data transmission systems. Phase noise adds to overall system noise increasing the bit error rate and may cause a cycle slip in carrier or data clock recovery.
Conventional phase locked loop frequency synthesizers exhibit better frequency agility using higher reference frequencies. This is due to the fact that phase locked loops generally require several cycles to acquire (lock) onto a signal. At higher frequencies, more cycles are available in a shorter period of time.
In conventional systems, the phase locked synthesized frequency provided by a frequency synthesizer either has many fine steps with high phase noise or has low phase noise with very limited tuning step size. More specifically, the patents listed below disclose conventional synthesizers that cannot provide both low phase noise and synthesized frequencies having many fine steps at the same time. None of these conventional systems provides both low phase noise and synthesized frequencies having many fine steps at the same time.
The prior art patents referred to above are identified as follows: U.S. Pat. No. 4,940,950 entitled "Frequency Synthesis Method and Apparatus Using Approximation to Provide Closely Spaced Discrete Frequencies Over a Wide Range with Rapid Acquisition," issued to Helfrick, U.S. Pat. No. 4,965,533 entitled "Direct Digital Synthesizer Driven Phase Lock Loop Frequency Synthesizer," issued to Gilmore, U.S. Pat. No. 4,912,433 entitled "VCO Controlled by Separate Phase Locked Loop," issued to Motegi et al., U.S. Pat. No. 4,234,929 entitled "Control Device for a Phase Lock Loop Vernier Frequency Synthesizer," issued to Riley, Jr., U.S. Pat. No. 4,388,597 entitled "Frequency Synthesizer Having Plural Phase Locked Loops," issued to Bickley et al., and U.S. Pat. No. 4,912,432 entitled "Plural Feedback Loop Digital Frequency Synthesizer," issued to Galani et al. Of these references, the Bickley et al. and Galani et al. patents disclose plural phase locked loop synthesizers, and are considered pertinent to the present invention.
The Bickley et al. patent employs three phase locked loops to achieve synthesis. The synthesizer includes a first phase locked loop comprising a mixer and a phase detector. A second phase locked loop having a programmable divider supplies a reference frequency in predetermined steps to the mixer, while a third phase locked loop provides a reference frequency in predetermined steps to the phase detector, which steps are different from the steps provided by the second phase locked loop. Also, in a preferred embodiment, a fourth phase locked loop provides a reference signal to a mixer in the third phase locked loop to reduce the operating frequency therein and the output of the fourth phase locked loop is mixed with an output from the first phase locked loop to extend the range of the synthesizer.
The Galani et al. patent discloses an indirect digital frequency synthesizer adapted to produce a signal having a selected one of a plurality of relatively closely spaced frequencies and having a relatively fast frequency switching time. Multiple feedback loops are fed by reference frequency signals whose frequency is greater than the desired frequency separation provided by the synthesizer. The bandwidth of each of the feedback loops is less than the frequency of the reference fed to each loop, and achievement of frequency separation less than the frequency of either of the reference frequencies enables each of the feedback loops to have increased bandwidth and therefore reduced frequency switching times and increased noise suppression.
In order to advance the state of the art as evidenced in the above-cited patents, U.S. Pat. No. 5,150,078 entitled "Low Noise, Fine Frequency Step Synthesizer" issued to Steven S. Yang, et al. and assigned to the assignee of the present invention, discloses a frequency synthesizer that achieves low phase noise and provides for synthesized frequencies having many fine steps, and provides a low phase noise frequency synthesizer with fine frequency step tuning. This synthesizer provides for half-integer digital frequency dividing, VCO frequency offsetting, and local oscillator harmonic mixing using two phase locked loop circuits. The first loop generates the required frequency steps, while in the second loop the signal is divided by a fixed number to reduce both the frequency step size and to reduce the phase noise. The second loop output is divided by two, and then mixed with the third harmonic of the reference frequency to generate an offset frequency that is locked to the low phase noise frequency of the first loop. The present invention is an improvement to this synthesizer that provides for wide-band frequency operation.
In view of the above, there is a need in the art for a frequency synthesizer and synthesizing method that exhibits good frequency agility and low phase noise, and provides many channels, thus permitting wide band operation.